Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
FIFO problem
Hi guys ,
I have a different Solution for the same question .
As the Qst says at rate of 50 bytes in 100 clks , and the max rate is 7 per 10 clks ,so we need minimum of 71 clks to complete 50 bytes .
and these 71 clks can be at any stage like 0-71 , 10-81 ,20-91,29-100,
After...
Hi
First let me now ..what u want to implement .is than an endpoint/Root complex . u want to implement a BFM or RTL IP . I suggest u to read Mindshare and then start to implement . If u have any doubts feel free to ask .
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
