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1) In DC do the following:
list_libs
Based on output above, locate the library name, should be on the same line as your library file name. Then do:
report_lib lib_name (example: report_lib class)
This will give some basic info on the procees used. For detail process information. you...
eeeraghu,
Once you have the netlist, check if the netlist meets your timing constraints i.e. setup/hold. You mentioned your design has critical path - every design will have a critical path, what you have to do is check if this path is meeting your timing constraint. If yes - then job done, go...
Re: Where does STA comes
STA comes after you have done logic synthesis and also after place&route.
You can use STA when you have a gate-level netlist.
Use STA to check for setup, hold and pulse width. Basically use it to check if your design meets its timing constraints.
synopsys ccss deadlock
CCSS is quite okay for Architecture design. Its a good choice if you use VCS for HDL simulation as CCSS integrates well with it, and you can do HDL co-simulation quite easily. Not sure if it works well with other HDL simulators.
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