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If you are doing LEC between rtl and netlist hierarchical lec is recommended since it works and divide and conquer strategy. Flat lec will be time consuming especially if the design is huge. For netlist to netlist comparison flat can be done.
Hi HTA,
Thanks for your response! I went across few books and got to know AND OR are non-inverting and XOR is neither inverting nor non-inverting. I was curious on the logic behind this though. Let me know if you can give me some insight on this?
Thanks!
Hello,
I would like to know more on inverting and non-inverting gates. For ex: NOT gate is inverting. How is it explained for AND OR and XOR gates.?
Thanks in advance
Re: first time going to make a chip . need suggestions whereever possible ???
Why have you not defined clock groups? I would suggest you to revisit synthesis constraints once.
Also now you have synthesis script templates from Synopsys/Cadence sites. You can download them and modify accordingly...
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