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3-8 decoder verilog
The schematics seem to be correct. But it is always advisible to check the gate-level netlist after the systhesis step. I don't know about the bugs in Design Analyzer as I do not use it very frequently.
energy delay product
I would like about the vilidity and usefulness of energy delay product and power delay product? Which of them is a better metric for designers?
In SRAM cells, we usually precharge the bit lines. We may use the p-type devices to precharge to full VDD. But does it improve only the writes and reads for logic 1, and makes slow memory access for logic 0?
How can we handle the situation?
clock and power routing
If the power and ground line is routed close to the clock distribution circuitry, what can be the effects?
Added after 3 minutes:
Its effects on noise margin, system performance...etc??? I don't have proper answers to these.
Hi can anyone give me the value of the wire parasitic capacitance for a lenth of 1mm in 90nm technology.
The value that I am having is around .2pF/ mm. But, it seems to be wrong.
Consider metal layer 4-7
Thanks
should be either a string or a symbol
Hi
I am working with cadence tool. I am using schematic editor with the 90n technology, but while simulating I am getting failures. With the .18u and .25u the things are fine. Can anyone help me in this regard.
The log message is as follows:
w...
Re: delay in digital domain
can you be a bit more specific....
If it is a real design, also the clk freq. can be suitably adjusted....may not be applicable always. You can also look for retiming....
Re: implement counter?
It seems that you want to operate the counter at high frequencies...
An asynchronous design seems to be a good choice for the same..
Consider a ring counter or a johnson counter....
automatic detection of multi-cycle path
Dear friend
I am searching for some free open source tool, to detect the multicycle paths.. for medium size sequential ckts..
Can anyone help me in this regard..
The fishtail products are not open source...
false path example
Dear folks
Can anybody help me with some tool or program that detects the presence of multicycle and false paths in digital circuits
multi-cycle path and false paths
Hi
I am doing a project on determining the existence of false paths and multicyle paths present in a circuit. Is there is software available for giving this information if the circuit netlist is given?
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