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Recent content by SparkingDog

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    How to Specify and Tolerance a "Sharp" Point

    I need to have an electrical probe machined; but I am unsure how to specify my requirements. I am an electrical engineer with only moderate mechanical knowledge. The probe will be machined from 0.125" diameter stainless steel round stock. The last 0.25 inch before the point necks down to a...
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    How to avoid audio coupling between channels when designing a PCB?

    I concur with jiripolivka. My emphasis: Watch out for shared impedances, particularly on power and ground. Many audio ICs put both channels in the same chip so you can't physically separate them. You want the power supply impedance at the audio ICs to be as low as possible. Use copper...
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    Is my High-side MOSFET Really Off?

    That is very helpful. I think I will use 100mV/decade for design and just keep an eye out for any risks or contrary results. I also suspect that typical max leakage specs may be overly pessimistic (it's suspicious that it is so often 1uA) - any insight about that? For example using my...
  4. S

    Is my High-side MOSFET Really Off?

    Thanks that is just the kind of authoritative source I was looking for. Unfortunately the highlighted section in the link only gives an example value for "n". What is needed is a maximum practical value for "n". At the bottom of the linked page the author mentions a minimum value for "n"...
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    Is my High-side MOSFET Really Off?

    You might be right; but, in the absence of specific authoritative information to the contrary I will continue to hope for a solution. These are my reasons: 1. Much of the process variation is accounted for by the Vth spec. It is a worst case that is tested in production. It provides a worst...
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    Is my High-side MOSFET Really Off?

    Again, my question is about the properties of FETs not about a solution to a specific circuit. But responding to your suggestion: A CMOS IC running off battery voltage to control the P FET could not be connected to logic powered from the regulated supply without level translation - probably a...
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    Is my High-side MOSFET Really Off?

    The question is about FETs in general - not my circuit. But the problem is that, generally, if you are building low power circuits from discrete FETs you must use high value resistors as pull-ups/pull-downs. Ids leakage of even 1uA creates significant voltages across those resistors...
  8. S

    Is my High-side MOSFET Really Off?

    I realize that the graphs are for typical values. I was just surprised by the orders of magnitude difference. Also I was once told by an App Engineer (about a microcontroller) that the 1uA leakage current spec in their data sheet was just a convenient tested limit and not the actual expected...
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    Is my High-side MOSFET Really Off?

    I am designing a real high-side switch circuit but my questions really apply to mosfets in general. The datasheets for discrete mosfets generally specify a Vgs Theshold (example: -0.45V @ Ids=250uA) and an Off leakage current (example: Ids<1uA @ Vgs=0V). In my circuit it is not practical to...
  10. S

    Cost Effective Banana Jack Solution

    I am trying to come up with a low cost - and no tooling solution to adding a vertical banana jack to my PCB. No tooling because I'm starting with a small batch. But I hope to ramp up; so, it should be scalable too. I might find a dedicated connector that works but that would greatly constrain...
  11. S

    OPA355 with excessive and asymetric overshoot

    This is an image of the layout if that helps. - - - Updated - - - This is the first design I have done with a bandwidth this high. I would appreciate any insight from those with more experience. Is it typical that the stray capacitance cannot be reduced to where a feedback cap is...
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    OPA355 with excessive and asymetric overshoot

    What in the layout could cause asymmetric overshoot? I would be grateful even for speculation. I believe I have been very careful in my layout. Tight placement of components; removal of planes beneath the output and feedback nodes; multiple decoupling caps (0.1uf & 1uf) between the supply...
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    OPA355 with excessive and asymetric overshoot

    I am stumped. I have an VFA (OPA355) ckt configued with gain=+2. Rf=499ohms, Vs=+/-2.5V. I have done everything I can think of to minimize stray capacitance. The amp has good decoupling. The amp is currently unloaded. The Problem: When I apply a 0.5V, 10Mhz square wave to the input, the...

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