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Recent content by spandus

  1. S

    Error while simulating the system verilog code using questasim 10.5 version

    Hello Dave, please find my code below: //COUNTER DESIGN //D FLIPFLOP module dff(clk,reset,din,dout); input clk,reset,din; output dout; logic dout; always@(posedge clk,negedge reset) if(!reset) dout <= 0; else dout <= din; endmodule //COUNTER module ones_counter(clk,reset,data,count); input...
  2. S

    Error while simulating the system verilog code using questasim 10.5 version

    Hello All, can you sort out the mentioned error while simulating the system verilog code. Thanks Spandana
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