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Recent content by sp.bhuvana

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    Need documets related to extraction of Inductance using Cadence Assura

    Hi, Iam working on LNA, When i do post layout simulation, I found that Inductance effect not taken into account like prelayout simulation. is it possible to extract inductance using Assura??? If so, Iam in need of Tutorials or documents related to Assura parasitic extraction.. I kindly request...
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    Post layout simulation results differ from prelayout simulation- S21 is negative

    Hi, As u said, i have increased the thickness of routing lines, my gain increased to positive(s21=7dB(In prelayout simulationS21 = 20dB); but frequency shifted to 7.9GHz)... still working on it... Thank you...
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    Post layout simulation results differ from prelayout simulation- S21 is negative

    Hi, The Layout of LNA is designed for 5GHz Herewith i have attached the LNA layout and RCX image for your reference, Kindly check it.. Pls tell me what should i do???
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    Post layout simulation results differ from prelayout simulation- S21 is negative

    Hi, Iam a beginner in cadence Virtuoso... Iam working on LNA, In prelayout simulation, S11 = S22 < -10dB; S21 = 20dB; S12 <-30dB; In post layout Simulation, S11 = S22 < -10dB; S21 = -10dB; s12 < -30dB Iam getting negative gain... Can anyone tell me what may be the reason for negative gain...
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    DRC Error: N+SD Iso Psub tap spacing must be <=10.0 um

    Hi Erikl, Actually to the left of NMOS is Nwell Tap(Nwell with Nimp). If i do not connect the Nwell tap, iam getting the DRC error stating that "NBuried Stamp_error Float" as shown in the picture. And Also as u said, i have connected Psub tap nearer to Nwell, still same error exists... What...
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    DRC Error: N+SD Iso Psub tap spacing must be <=10.0 um

    Hi Erikl, Sorry for the delayed reply. Herewith i have attached the image of my problem.
  7. S

    DRC Error: N+SD Iso Psub tap spacing must be <=10.0 um

    I have already attached Psub tap to N+SD... Still same error exists... And also tried by attaching IsoPwell tap... still getting same error... Kindly help me...
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    DRC Error: N+SD Iso Psub tap spacing must be <=10.0 um

    Hi, Iam new to Virtuoso Layout L. I tried to simulate LNA using nmoscap from gpdk180. Iam getting an DRC error stating that "N+SD Iso Psub tap spacing must be <=10.0 um". Kindly help me to clear that error
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