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Recent content by sowmiya

  1. S

    Query reg multiple module definition in verilog

    Hi, I have a case wherein there are 2 defintions for the same library cell in verilog. The incorrect definition file is present in the library dir from which I read all the other files using "vcs -y <dir path> " option. But the correct file is present in a different area. I want the simulator...
  2. S

    Phase noise to jitter conversion

    Thanks for the reply. But do you have any document or explanation to support this? I want to get a clear picture about this.
  3. S

    Phase noise to jitter conversion

    phase noise to jitter conversion Hi, I have an RC oscillator circuit for which I need to calculate the Peak-peak cycle jitter. I am using Spectre simulator. But I cannot just run a transient analysis and find the same since the models I am using does not comprise the noise component. Hence I am...
  4. S

    Generating random nos in verilogA for simulation in Finesim

    finesim I am currently modeling jitter in verilogA. For this i need to generate random numbers. This model is to be run with finesim as the simulator. Can anyone suggest any way to do this as finesim does not support $random function unlike spectre?
  5. S

    Need IEEE paper Crippa, P.; Conti, M.; Turchetti, C.

    Re: Need IEEE paper Thank you Charles.
  6. S

    Need IEEE paper Crippa, P.; Conti, M.; Turchetti, C.

    Need IEEE paper A statistical methodology for the design of high-performancecurrent steering DACapos;s Crippa, P.; Conti, M.; Turchetti, C.
  7. S

    convergence problem in OTA verilogA model

    veriloga ota I am modeling an OTA with VerilogA language. As i want a single pole system, I am using the laplace_nd function in VerilogA to model the transfer function of the single pole OTA. When i simulate this model alone in spectre it gives me correct result. But when i am using this OTA in...
  8. S

    Problem with $table_model in verilogA

    verilog a table_model Hi, I am having problem with using the $table_model function in my verilogA code. I initially tried with an example code i found on the net. It goes this way: module table_resistor (n1, n2); electrical n1, n2; analog begin I(n1, n2) <+ $table_model (V(n1), V(n2)...
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