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Hi Tony,
Do you have any information on harmonic rejection per se? This is what I've gathered from reading around: LO is delayed and advanced by 45 deg (the amplitudes are also scaled to sqrt(2)) and mixed with the incoming signal. So we essentially have three LOs 45 degrees apart mixing with...
Hi all,
I'm new to RF design and could use a book covering the math and basics of harmonic rejection mixers.
I'd appreciate it if someone could suggest one to me.
Google search returns papers that assume prior experience in the field already. I'm really looking for introductory material on the...
Hi,
Using EET I derived the following symbolic expression
C1*C2*C3*R1*[R2 + (RL //R3)] (R2 //R3//RL)
I know that the expression reduces to this
C1*C2*C3*R1*R2 (RL //R3)
I don't know where to begin to reduce my expression to get the final answer. Can anyone help me? Are they identities to...
Can an RF person explain why we need multi-phase LO generation for the mixer.
I can't find an introductory resource on the subject. Any textbook reference would be really appreciated.
Thanks
Hi All,
I'm simulating a transistor level, continuous first order delta sigma modulator and need some clarification on the my gm-c filter.
Simulation is all in Cadence.
The input frequency of the DSM is 10hkz so what should the 3-db cutoff frequency (not my unity gain frequency) of my gm-c be...
Hi FvM,
I did as you suggested. Let me see if I'm interpreting this righ: drain-source voltage of M2 get shorted while drain source voltage of M1 becomes high impedance which is counter-intuitive and seems to contradict the following analysis. I would expect M2 to be highZ when ip is high -->...
Hello,
Please refer to the images attached.
I'm hoping someone can shed some light on this because I'm really confused about this. I have a simple diff pair where I sweep, one input (ip) and hold the other (in) at vdd/2. At ip = 0V, I would expect the entire bias current to flow through the...
Hi Klaus,
I had to take some time to resolve some circuit issues I was having. Anyway, let me clarify:
1) I built and adc in cadence virtuoso with real components so the output stream I obtain has real non-idealities.
2) I processed the output stream with ocean and computed my SNDR with...
Hi All,
Given a cmos circuit, is there a setup that can be used to determine the range of inputs for which the devices remain in saturation?
In other words, how do I make sure that my mos devices never leave saturation for a certain input range?
Thanks
Thank you amaximus. Any thoughts on how wide my frequency range from the center should be for my sndr calculation? Any rule of thumb?
I'm currently using this piece of code and my SNR is awful -26dB which can't be right.
Thanks.
signal_bins=[0:(nb-1)];
inbands_bins=0:NFFT/(2*OSR)...
Hi All,
This is my first ADC and verifying it is proving to be more difficult then actually designing the sub-blocks.
I have been able to do a transient simulation in cadence (
Spectre) and have successfully imported the data into matlab.
This is where I'm encountering most of my HEADACHE.
1)...
Hi All,
This is my first ADC and verifying it is proving to be more difficult then actually designing the subblock.
I have been able to do a transient simulation in cadence (spectre) and have successfully imported the data into matlab.
This is where I'm encountering most of my headache.
1) I'm...
Hello,
Could someone shed some light on this for me?
I was under the impression that devices from the analogLib library did not have to have models. I just built a simple circuit with a pmos and nmos from the analogLib lib and it fails to simulate in spectre. Problem? Spectre says that the...
Thanks for the reply,
I have done a tree of both the layout and the schematic and neither file contains "probe" in it. The layout is a port so who knows what it contains but in all my years of doing layout, I've never used a layout probe and don't know what it is or its use.
I don't think this...
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