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Recent content by sonika111

  1. S

    Multiplication in vhdl

    Hi there How to mutiply say 16 bit signed number with 8 with signed constant using adders to get the result in one cycle (in vhdl)? Thanks very much
  2. S

    Learn cryptography/emcryption in VHDL

    Hi guys I want to learn cryptography/encryption in vhdl ( as applicable to FPGA's). I don't know where to start? Any good resources, pointers and help/advise to learn that would be appreciated.... Many thanks
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    vhdl problem debug help please

    Thanks very much, I will give it a go if not 1 will try writing in 1 process FSM style
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    vhdl problem debug help please

    Thanksvery much for your reply Its value remains 1. I don't know why? What library should I be using ? How do I change the above code so that I can introduce a delay of a=say 3 clock pulses between S0 to S1? - - - Updated - - - I tried putting if (Reset = '1') then cState <= S0; elsif...
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    vhdl problem debug help please

    signal count :std_logic_vector(1 downto 0):= "00"; -- Enumerated type declaration and state signal declaration type States is (S0,S0a, S1, S2, S3,S4); signal nState, cState: states; begin state_reg: process(clk, Reset) begin if (Reset = '1') then...
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    Good verilog or vHDL book for implementation of mathematical operations

    Thanks very much. I would appreciate if you could suggest the name and author of some good dap book for fpgas
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    Good verilog or vHDL book for implementation of mathematical operations

    Hi Guys Can you please suggest a good verilog or vhdl book on implementation of optimised mathematical functions such as convolution, matrix multiplication etc... (or any other resource) Thanks very much
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    Verilog testbench help!! (bit urgent)

    Sorry this is confusion and I am not a troll please I would try to explain again and you guys from fresh try to help me genuinely:- Problem: I have to read a continuous hex file such as 0000 ffff 0000 ffff acac 0000 .... ....... etc etc and assign the value read to tb_b = data[15:8]...
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    Verilog testbench help!! (bit urgent)

    How do I send the txt file?? If that is needed I would send?/ but I have already tried telling it has 32 bit hex values in a row 0000 0ffff acac 0000 0000 bbaa ...... ...... ( so many of them) Thanks
  10. S

    Verilog testbench help!! (bit urgent)

    I am nearlly at the end and thanks for all your help. If you guys can plaese help in these three things. 1. The problem above which is critical 2.display strings from my txt file which are in "Blab blah Blah". 3. I am unable to see the variables from the testbench which are not on the ports. I...
  11. S

    Verilog testbench help!! (bit urgent)

    Thanks for all your replies. The things you can help without helping the code can you please help those like 1.the problem above 2. display strings from my txt file which are in "....................". 3. I am unable to see the variables from the testbench which are not on the ports. I would...
  12. S

    Verilog testbench help!! (bit urgent)

    I can't see them on object viewer either. Also I am unable to display strings from my txt file which are in the form "Blah Blah Blah ". Mnay thanks - - - Updated - - - Right .... I have a big txt file containg 32bit hex value repeated in a single continuos line like 0000 0f0h 0acc ...
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    Verilog testbench help!! (bit urgent)

    Thanks very much for all your help with the little information that I could give. Really appreciate your help and apologise that I could not share much I am unable to display strings from my txt file which are in "....................". Also I am unable to see the variables from the testbench...
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    Verilog testbench help!! (bit urgent)

    Thanks very much TrickyDicky for all your help and everyone who tried to help On another note; I have another problem, in my simuation some of my reset signals to from 0 to H state and they are causing Xes in my solution. Can anyone plaese advise me what can I do that it dosen't go to H state...
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    Verilog testbench help!! (bit urgent)

    Thanks very much TrickyDricky. The problem is in the original testbench the same things worked while assigning values to inout signals directly and it didn't complain but the verilog one complains when you assign the directly. (so the need to probe the enables)?? I really don't know how to deal...
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