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ok..so what do you say..i guess the output is correct as can be compared by the link also(tutorial by bonnie baker).but i am not able to interpret it correctly
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No, I have'nt used any D/A converter.
the Ist waveform to left is the ADC modulator output. then it is fed to the decimator. 2nd waveform (right) is decimator's output. i was thinking it to be wrong but this matches the decimator output of the link (fig 1)...
hello all
the decimator output should not be as shown..but you know when i simulated output for 2nd order SD ADC the output of decimator actually comes out to like this only. things are write but do not understand why and how
thanks for ur replies all
hello
what is confusing me is the figure 1 block diagram of https://www.ti.com/lit/an/slyt423/slyt423.pdf
the output of digital filter. should it not be just the filtered output of previous section
thanks in advance
dear crutschow
loads of thanks for your reply.it was a great help indeed
1. i got the solution to problem 1
2. i am resending the link to problem 2 https://www.ti.com/lit/an/slyt423/slyt423.pdf
kindly check fig 1 block diagram
thanks in advance
thanks a lot for your reply but could you please explain this to me.
1. kindly check the link https://blogs.mathworks.com/pick/2013/05/24/delta-sigma-toolbox/
this and many other show the output of modulator as series of 1 and -1 instead of 0s and 1s
2. pls see the link **broken link removed**...
hello all
I have two queries on sigma delta ADC
1. While going through its material i found that while some show that the output of the modulator is series of 0s and 1s, some show it as series of 1 and -1.
Which is correct
2. The output of decimator is shown as a discrete signal and not...
thanku for your help barry...but my query is for the example you quoted ,why output is 1 MHz/no.of samples per cycle
your answer would be of great help
thanks for your reply barry..a very basic question, which may sound absurd to you but i am working on my basics..how is output frequency input =1MHz/100 where 1 mhz is clock frequency and input frequency is 100..
tonns of thanks
what is the relation b/w no.of samples/cycle and a sine wave.
as I am increasing the no. of samples/cycle it appears the sine wave appears to have less frequency (more loose, to be clear) for the same time period.i figured out everything but could not get the exact reason.all is explained on the...
also as i calculate snr from the above code ideally the complete range of snr for different OSR of the second order sigma delta modulator should be high as compare to the ist order sigma delta modulator.but m getting lesser SNRs for 2nd order than ist orders
hello
i was simulating of a first order adc using code given in book of richard scherier. for calculating SNR he uses (page 265)
snr = calculateSNR(spec(1:ceil(Nfft/(2*OSR))+1), tone_bin)...
where spec is spec = fft(v.*ds_hann(Nfft))/(Nfft*(nLev-1)/4);
well i don't understand this.if i...
i guess since we want the frequency to be around a certain bin say 31 in above case hence we select tone bin as the frequency to be selected over the entire nfft length...pl correct if i am wrong
ya i would have posted the complete program..actually i was talking about delsig toolbox in which all sine wave assume the same formulae...one of the example is (which quantizes the sine wave using delsig toolbox)
nLev = 8; % Number of quantizer levels
M = nLev-1 % Number of steps...
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