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Hi,
This is in reference to annotating delays through sdf on a hierarchial design.
I have an hierarchial design with three subdesigns. I want to annotate the delay of these three subdesigns to the top design.
I have written out sdf files for each subdesign through design compiler.
Now, when...
Hi,
Consider this scenario.
Consider an inverter with an input net and an output net connected it. There is a neighbouring net which is actually a floating net and there is no transition on this net.
What is the effect of this floating net in terms of signal integrity on the nets connected...
negative hold time flop
Negative hold time is generally seen where a delay is already added in the data path
inside the flop.
Assume the flop which foundry gives us as library part has ports named as CLK-port,
Data-port. Now treat this as a wrapper. Inside this we have the real flop whose...
Hi
Let’s say there enough routing resources available, timing is fine, can you increase clock buffers in clock network? If so will there be any impact on other parameters?
How do you optimize skew/insertion delays in CTS?
What are differences in clock constraints from pre CTS (Clock Tree...
Hi,
Can we add a delay buffer on the clk capture path to reduce the setup slack value (i.e. I am trying to tweak with the launch clk arrival time so as to delay the data required time) when all attempts to reduce the setup slack are invain like resizing gates, buffer insertion, placement eco...
Re: pwr consumption
HI,
By worst case condition, I mean everything on the design is switching. Moreover the design is digital.
I derived the pwr consumption of 3 W using DC through setting switching activity.
Thx
snr_vlsi
pwr consumption
Hi,
If the power consumption value is 3 W reported under worst case conditions, what can be the pwr consumption value that can be assumed under ideal conditions for power planning.
Thx
snr_vlsi
Re: power mesh
Hi,
As I am not having any separate tech. file for extraction, I am unable to find the values.
I would be very glad if you could share the info. you are having even though it is outdated, as it would give me a chance to check with my power calculations. I am not currently too...
hi,
can anyone share how OCV timing analysis is done with a single library (suppose max lib). What is the derating factor to be set for a process node like 180nm.
How is set up and hold analysis carried out.
Thanks
snr_vlsi
Hi,
Currently I am trying to do power mesh calculations for a design. The lib. does not contain the following values.
I shall be glad if anyone can pass me on the values of any fab (tsmc, csc, ibm or others)
Current Density for a 4 metal layer 180 nm process
Sheet Resistance
Max. Current...
shift and capture in dft
Hi Badola,
Thx for your reply.
Can u give me some more covering atpg like pattern generation, pattern compression, and standards like jtag, ieee1500 etc
thx
snr_vlsi
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