Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by snowgal

  1. S

    how single nmos/pmos Directly go to saturation

    @ eladla , in the graph you can see clearly at vin=0.7v which is the threshold voltage , the vout starts decreasing with increase in input as the transistor starts entering in to the sat , b/w the points 0.7v to 1.8v transistor is in sat where it satisfies theoritical eqn too VDS >= vgs-vt
  2. S

    how single nmos/pmos Directly go to saturation

    Hi , I am attaching the graph , in the graph also u can see tht from cutoff it moved to sat , https://obrazki.elektroda.pl/60_1284835907.png the marker was placed at the intersection of the input and output , here input vgs varies from 0-5v and vdd at 5v , thanks swetha
  3. S

    Regarding fingers in MOS transistors

    Thanks a lot for helping me.. please let me know where can i post to know more about cadence... thanks in advance Regards swetha
  4. S

    Regarding fingers in MOS transistors

    Hi keith, thanks for reply , I am using cadence , W/L is the width/length of the single finger but i need to know more about exact difference between fingers and multiplier... 5(10/25), in this case whether 5 is multiplier or fingers.... Thanks Swetha..
  5. S

    Regarding fingers in MOS transistors

    Hi , In the design , it was given as 5(10/25) , which means 10 =width and 25 = length, I am confused whether 5 represents the no of fingers or multiplier , in schematic i assumed it as the multiplier and designed , and i tried with fingers also , but the output didnt vary. Now in designing...

Part and Inventory Search

Back
Top