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Recent content by snleo

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    Large IOPATH delay in SDF file writtenout by DesignCompile??

    Re: Large IOPATH delay in SDF file writtenout by DesignCompi Thanks a lot, pete_lu. All the uncorrect delays are from CLK to Q. In my timing report of DC, all the delays are correct. Could you tell me how to get the EMA setting of my SRAM/ROM library? Thanks.
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    Large IOPATH delay in SDF file writtenout by DesignCompile??

    After compile , i write out sdf file with write_sdf in DC, but in sdf file, the CLK to Q IOPATH delay values of SRAM, ROM & some DFF are 600++ , obviously something wrong, but the report of report_timing is correct, what is wrong ? Could anybody give me some advise ? My DC version: Version...

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