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Recent content by snakebites

  1. S

    HDL Entry vs. Schematic Entry Tool?

    I use verilog entry, because I lerarned C++ and it's very easy for me to grasp verilog.
  2. S

    Bi-CMOS or CMOS layout - how?

    You will find a book named"analog bicmos design practices and pitfalls" in book zone. It may help you.
  3. S

    How to add a component from Xilinx Core Generator?

    I think you should get a core update packet from Xilinx if the problem you described was a version issue.
  4. S

    model\sim Vs Active\H\DL

    modelsim,waveform editor ,key ActiveHDL is easy for newbie, but I think Modelsim has some special functions.
  5. S

    Question about two frequencies in USB DPLL design

    DPLL design question In DPLL design, two frequency should be input: one is reference frequency, the other is the frequency to operate counter and inc_dec module, which is much higher, 8 times(or higher) of reference frequency. So in the USB design where the data rate is 12Mb/s or 1.5Mb/s, there...
  6. S

    How can calculate the sine an cosine function by using FPGA?

    sine lookup table fpga Xilinx has IPcore named CORDIC. It will can be configured as sin, cos, arc tan, square root function.
  7. S

    Post Synopsys Synthesis Simulation Using ModelSim

    post synthesis is simulation If you use Xilinx core,then core lib is also needed.
  8. S

    What software is typically used for Xilinx FPGA development?

    If you have ambitious timing requrements,I think Amplify is better. I use synplify(amplify)+ISE+modelsim
  9. S

    VHDL vs Verilog which more popular?

    I think we should set up a vote to see which language is more popular.
  10. S

    How to perform post-synthesis sim with synplify results?

    The output of synplify is .vm. How to perform simulation with .vm files? I just change .vm into .v,and perform sim in modelsim.Neither using testbench nor macro files(.do) can I give stimulus to input ports,such as clk, so the results are either 0 or x. BTW, modelsim didn't generate any error...
  11. S

    Verilog HDL Synthesis A Practical Primer

    Thank you! That's really good !
  12. S

    What's the speed grade for FPGA?

    fpga speed grade Such as -6,-5s1? Thanks.
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