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Recent content by smsskil

  1. S

    Need some tutorial for golden netlist flow

    I know. I mean that after RTL coding in FPGA, I need to do generic synthesis and technology synthesis. Then I need to verify synthesized netlist. Actually I dont know how the practical flow is running when people do the same things as I learn now.
  2. S

    Need some tutorial for golden netlist flow

    I'm a beginner of ASIC. Recently I have complete the RTL coding in FPGA, now I want to transplant it to ASIC. But there is no whole flow for getting golden netlist. If there has any resources for it? btw,it's better if the resources using Genus or RTL compiler. Thanks a lot
  3. S

    Encrypt verilog with ablity to synthesize in cadence tool

    Hi jbeniston, I have searched pragma protect,noticing that there are many posts mention ncprotect. But the question is,can ncprotect output file that can be synthesized? Or there are other software to do this...
  4. S

    Encrypt verilog with ablity to synthesize in cadence tool

    is it possible to encrypt verilog code but can be synthesized in cadence? I need to give my design to customer for his integrating. But I don't know how can i protect my file Any help?
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