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Okay, I am still stuck :(
That was on my mind.
So in the read module I have changed this part
6'd33 : DATA[7] <= SDI;
6'd34 : DATA[6] <= SDI;
6'd35 : DATA[5] <= SDI;
6'd36 : DATA[4] <= SDI;
6'd37 : DATA[3] <= SDI;
6'd38 : DATA[2] <= SDI;
6'd39 : DATA[1] <= SDI;
6'd40...
Correct, the turns a 50 MHz clock into the I2C clock SCL clock and operations counter.
Should I change the example to make a slow clock outside of the modules? Is it better style?
I will give this a try.
I agree.
Its just this write sample is the only one I could find thats a complete...
Hello
I am learning FPGA's using a DE0-Nano Cyclone IV board from Terasic.
Using verilog and I2C, I can write to the boards onboard 24LC02B I2C 2K EEPROM, but I cannot read the EEPROM. So I can read but not write.
The reason I know I can write to the EEPROM, is because after writing, I use...
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