Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I am reading the image using ADV7123 video converter, And i am using an IP core from Qsys to get the input from reverse camera. i am storing this image into SDRAM, and i am viewing it through VGA port. What i meant by moving object is that the camera stays still but moving objects in a convey...
I am using a reverse camera plugged in to composite input. I want a single frame for analysis and a clear one. Since it is a CCD sensor, it should capture all the pixels at once. Which should give a clear image. But i am only getting a blurry image. I also using the Video-in IP core and control...
I want to use the "DMA's Front and Back Buffer Address Translator " IP core, but i can't find the description of the register map of it.
Does anyone have information about this? Any help would be greatly appreciated
The fifo i am using is a template from quartus. My ultimate goal is also to change the clock domain. That is why i am using that template. Also Addr1 runs faster than addr2, so the condition "if (addr1 = addr2) then" will prevent overwriting the fifo and makes the addr1 go slower than addr2. I...
Hello everyone,
I want to transfer a frame from 143Mhz clock domain to 49Mhz clock domain to view the frames through vga,
For a test i tried to transfer a vertical and horizontal white lines to view through the vga port. But i am not getting it right.
What i expect is .
But what i am getting...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
