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ESDSolutions,
VDD-VSS clamp is being developed, The clamp is NMOS with RC triggering( RC connect to an inverter driving an NMOS clamp between VDD&VSS), as shown in figure. The process is 0.13um TSMC process. There are two structure NMOS clamp. One is non-silicided NMOS with 1.95um distance from...
Virtuoso is the best analog design platform.
Spectre and Hspice are the best spice simulator. Eldo is also powerful simulation tools.
Laker is the best layout tools.
Calibre is the best DRC&LVS tools.
Assura and Star-RC is the best extract tools.
VCD file (Value change dump file) is a wave-form file. It contains information about value changes on selected variables in a design. It can be generated by verilog simulator.
Saif file record the signal switching activity. It is only used to evaluate the power comsumption.
First dump a vcd file. Then use vdc2saif to convert vcd file to switching activity file.
Another method, when you simulating using NC, add a PLI in power compiler. I forget the name PLI. Using the PLI, a system task can be called in NC to generate switching activity file.
Now, some P&R tools can use clock skew to fix setup time violation. And some times, after cks, new setup time violations maybe occur. So, setup time violation should be re-fixed, after cks. But only few case, fix setup violation after routing.
In Cadence ADE, you can use hspiceverilog simulator to simulate verilog+schematic.
1 create a cell contain verilog file(using functional view)
2 create schematic view of test_bench cell connecting verilog cell and schematic cell.
3 create config view for test_bench cell
4 Open config view of...
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