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I have very interesting HBT devices fabricated on thin SOI.
The most interesting part is that by increasing substrate bias voltage, Rc decreases, breakdown voltage decreases, ft/fmax increases.
Now I am trying to build a circuit model for this device, unfortunately I am new to modeling. My...
Before you download the whole thesis, I suggest you download this small file to see the detailed content about this Thesis...thus you won't wast your points when you download the whole thesis.
regards
Shorse
Deleted.
/pisoiu
low drop out thesis
PhD Thesis
Title: Current efficient, low voltage, low drop out regulators
Author: Gabriel Alfonso Rincon-mora, also the author of the much-refered book "Voltage Reference".
Chpt 1: Introduction
chpt 2: System design consideration
chpt 3: Regulator topologies
chpt 4...
Thanks for your reply.
It is a 0.18 um technology, and I am working for college and I guess I won't worry too much about the error.
It is a bulk technology, and I don't know the best way to attack the leakage at high T.
Yes, I did a lot of high T measurement (DC +AC) on transistors, and I need...
I am working with a deep submicron BiCMOS technology.
I did some high T measurement on BJT, and the collector-substrate leakage is 75 nA at 200 C and 1.7 uA at 300 C.
One of my workmates has already submitted a bandgap reference ckt using Brokaw cell. My cadence simulation shows that the output...
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