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We have included Analog Devices AD7725 ADC in our last design, but we cannot succed to make ADC running. 16 ADCs are connected with parallel bus and controlled by Xilinx Spartan2 FPGA. I/O bus is driven with 3.3 LVTTL IO as ADC specification allow signals (all digital except clock) to be driven...
I agree, but such tool could be used to generate skeleton of the VHDL file and then add on features using hand coding. As I'm not experienced VHDL user ... I think this is a good way to start.
I'm developing for Xilinx Spartan II and the question is, which state-diagram tool to use (from which package):
1. ISE
2. Active HDL
3. Visual Elite
4. Mentor
I think the version we are looking for is
ChipScope ILE (not only PRO). BTW, how could
I access your download on BB site? I'm also
interested in ChipScope 4.2i ILE
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