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I have written a verilog code (PWM) to drive a servo motor (TG9e). The simulation result of the verilog code is as shown below.
In Figure 1 - input (In) is 'Logic 0' and in Figure 2 -input (In) is 'Logic 1'.
But, when I am downloading the verilog code to Spartan 3E starter kit and trying to...
To overcome this problem you need to do a small change in the DRC rule file.First go to /RuleDecks/Assura/DRC, then open
"G-DF-MIXEDMODE_RFCMOS18-1.8V-3.3V-1P6M-MMC-Assura-drc-2.10-p1.rul" file -> go to the last line which is "load( "./DRC/G-DF-LOGIC18-1.8V-3.3V-1P6M-Assura-drc-memory.rul" )"...
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