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thanks very much, but if you use dual slope, for the case of 9k samples/second, you must have a clock frequency of about 590 MHz (2^16*9000, because you must count down 2^16=65536 times to decide which level the sample is in), which is not quite feasible, is it ?
is this actually doable in 0.35 um or 0.5 um CMOS nowadays without calibration or trimming ? i do not want to do a sigma-delta ADC for this "threshold" resolution (16 bits, cause it's high, but not too high to keep successive approximation out of choice), can anyone give me suggestions ?
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