Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I am having some scripts for running a physical design flow. There I am having a script where limit for clock slew and data slew is defined.
Clock slew value is 0.200 ns
Data slew value is 0.400 ns
So my query is why do we have clock slew limit lesser than the data slew limit ? Does clock...
I am having some scripts for running a physical design flow. There I am having a script where limit for clock slew and data slew is defined.
Clock slew value is 0.200 ns
Data slew value is 0.400 ns
So my query is why do we have clock slew limit lesser than the data slew limit ? Does clock...
I am having some scripts for running a physical design flow. There I am having a script where limit for clock slew and data slew is defined.
Clock slew value is 0.200 ns
Data slew value is 0.400 ns
So my query is why do we have clock slew limit lesser than the data slew limit ? Does clock...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.