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Recent content by sivateja.m

  1. S

    clock frequency after floor planning and placement

    No, but change in your clock frequency affects placement and routing.
  2. S

    Calculations For Halo Width For Block Macro & Number Of Power Straps Required

    Hi, I tried google but couldn't get anywhere. Can you please explain how to calculate the width of the halo required while placing macro during floorplan and total number of power straps required during power planning along with mathematical equations if possible? Thanks & Regards, Siva
  3. S

    verilog for loop coding.i got error need endmodule due to for loop found

    Its missing generate .. endgenerate block module das (u,c,z); input [0:31]u; input [0:31]c; output [0:31]z; genvar i; generate for (i=0;i<32;i=i+1) begin assign c[i]=(u[i]&c[i]); end endgenerate endmodule
  4. S

    do functions synthesize to combinational logic?

    Hi, Functions are synthesizable. The above code will synthesize to latch because you are not defining the output when en == 1'b0. So when en is 1'b0, it will give previous value when en == 1'b1, which is a latch. Hope this helps!
  5. S

    immediate assertion in systemverilog (SVA)

    Hi Mina Magdy, I would like to answer few of the above queries related to Assertions .... 1. Immediate assertions works as the Blocking region but in Reactive region. 3. You cannot code immediate assertions in program block just like assign in module but you can make use of concurrent...
  6. S

    What does this command mean?

    Hi, uname prints the system information, -r prints the kernel version. The sed operation above used in pipeline is replacing whatever is present after first 3 digits like 1.2.3.4.5 --> 1.2.3 so uname -r | sed 's/\([0-9]*\. [0-9]*\. [0-9]*\).*/\1/' is same as uname -r. sed 's...

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