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Hi,
you can try this,
1. If der are different module in your project (work), Identify the timing critical module.
a. you can do this by P&R for each module.
2. try to do pipeline your logic.
Hi,
We know der are many library vendors, for eg,
a. TSMC
b. UMC
c. Samsung
d. IBM
e. Chartered etc...
consider a technology (45nm)
above mentioned library vendors will provide libraries for 45nm technology,
1. what is the difference between TSMC libraries with others?
2. Is der anything...
Hello,
We know der are many types of I/O standards like
1.LVCOMS
2.LVTTL
3.LVDS
4.SSTL I & II
5.HSTL I & II etc...
Usually what type of I/O will be used in chip, to say more clearly
1. if a chip I/O voltage is 2.5V, what type I/O standard will be preferred and why?
2. This will be...
Hi Every one,
Basically Full Custom ASIC is starting from scratch, but
1. Wen we go for full custom ASIC?
a. for a new technology
b. for existing technology (45nm), optimizing Power, Timing and Area etc...
c. for both case
d. other (specify)
can you share your...
Hi every one,
I am fixing transition violation in my company, I got some questions.
Transition fix between singe driver and single sink,
Basically we will decide size of buffer and we will insert buffer in between a driver and sink to avoid trans. violation.
der are different sizes of buffers...
Re: Warning: (vsim-3473) Component instance "i_rdy : xbip_pipe_v2_0_xst" is not bound
Hi Sckoarn,
Thank you for your valuable reply.
Actually I copied all the supporting files and compiled. Even then, at the time of simulating I am facing this issue. I thought of missing some files initially...
Hi,
I am designing CDMA Transceiver,
I got struck in Accusation and Tracking part :?, Can u suggest me some idea how to implement this part in CDMA.
If you have any data(files "pdf" or link), I will be happy:-) if you share with me.
Thank you in advance :-)
Warning: (vsim-3473) Component instance "i_rdy : xbip_pipe_v2_0_xst" is not bound
Hi,
I am trying to simulate a SIN and COS LUT table generated from core-gen.
1. I have created "Xilinxcorelib"
2. Corresponding files are compiled.
3. Wen I am simulating, I am getting this warning. (please...
counter vhdl
Whats the problem in it dude.....
u find the rising edge of every pulse and start count for every rising of the pulse.
silmultaniously u run another counter.... to count upto 1 sec. If one sec readched then u initialise your counter.
Do u have any idea of what will width of the...
Re: counter overflow
hi sau_sol,
1) What will overflow? when the counter reaches maximum limit time ie for 8 bit 0xFF for 16bit 0xFFFF
2) what will happen beyand that.
3) whats the disadvantages and advantages of counter overflow?
Flash Memory
I am having a basic question in flash memory. This question also applicable for EEPROM.
In flash memory MOSFET will have 2 gates [control gate and floting gate] and the a bit/voltage will be stored in between these two gates.
My question is even when the power off how the bit is...
error:constraintsystem:59
Hi,
I am trying to Interface DDR SDRAM with Spartan3. I am using MIG_V2.3 to generate Interface block.
When I am doing PAR, I am getting the following error.....
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