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Hi! The design now passes timing analysis. But its weird. When i do remove_design -all then rerun the script it fails sta, but when i do remove_design -all and remove_lib -all then rerun the script it passes sta. Which is correct and which is wrong? Why do they have different results? The...
Hi! I checked my sdc from pnr and the clock was already set as propagated there. I checked my timing analysis and the problem is the clock network delay for my launch register is 0, while for my capture register i have some value. That is why I get hold time violarions. Is it possible to have 0...
Hi again ! I read the man page of set_path_margin and I did not understand the description. What does this command do? Does is set target slack? Also I noticed that it has -to and -from arguments, does that mean I have to declare it on every violating path? Is there a way i can use it more...
Hi! thank you for your responses. I tried setting the clock as propagated and the slack became -0.01ns. Can I do that? Or that should always be the case? Thanks!
Hi!, I did place and route of a design and for the hold-time slack i got 0ns, but it says it met the timing. But when i read the design in primetime, then read sdc and spef, i get a hold-time slack of -0.27ns, is there anyway i can add extra slack during place and route, make it more than 0ns...
Hi! When i create a floorplan in icc i dont see any vdd or ground pins, are they hidden or should i add them? Will they be added in icc or in other steps? Thanks!
Hi, im trying to synthesize the openMSP40 processor using design compiler, using the saed90nm library, can anyone tell me why im getting this very large delay on the AND gate.. thanks!
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