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Both Xilinx and Altera provide a floating point square root function:
Altera's Megacore function: Altera Floating Point Megafunctions
Xilinx's CoreGen function: **broken link removed**
But I thought you needed VHDL? If all you want is a square root for Spartan-3, then I'd suggest you go with...
There is no such thing as an RS-232 port on a Spartan. I think what you're asking is: 'how do I route my design such that it uses the pins that connect to my external RS232 transceiver?'
Assuming you are using Xilinx ISE, you need to add a constraint file that specifies pin locations for each...
Latches are used in designs for specific purposes. Often, the use of latches is considered "bad practice" in a synchronous design (and synthesis tools will often give you warnings when latches are inferred).
However, latches are still important. As an example of where you might use one...
Yes, CORDIC can still be used for floating point, although it is not necessarily the best method.
What is the format of your FP numbers? IEEE single precision, IEEE double precision, or something else?
Again, I would say that the method you choose depends on your constraints: available...
Hi Praveen,
There are many ways to calculate the square root, and the method you choose depends on several factors:
- how fast you need to do it (clock speed and latency requirements)
- how much hardware you want to use (and what resources are available in your chosen device)
- how accurate...
Hi yadavvlsi,
I mainly do front-end, up to and including synthesis, then pass to someone else to do the layout. I then do post-layout gate level simulations.
My last chip was ~1 million instances, plus a lot of RAM.
I use ModelSim for simulations. Of course, ModelSim is single-threaded, so it...
Typically, in digital design, you would create your design in a hardware language such as VHDL or Verilog.
You can use a Simulation tool to simulate this high-level description, display waveforms, and so on.
A synthesis tool takes your VHDL code and converts it into mathematical equations...
Hi Bin,
I've recently done a TSMC gate level simulation.
Normally the gate library will be in the form of a big verilog file (or several files), and you need to edit your compile script to include this.
If you're using ModelSim, you need to invoke vsim with the -L option to point it at the...
I was wondering what kind of computers/workstations/servers are required these days for designing the latest digital ASICs?
I don't do many ASICs, but the last one I did was a 65nm job with a die area of about 40mm2. To do the gate level sims on that I used a 24-core Xeon blade and it needed 96...
I am just about to start an ASIC design, probably targetting TSMC 90nm.
I need some of my inputs to be LVDS, which seems like a fairly normal requirement to me, but there don't seem to be any LVDS I/O buffers in the standard vendor libraries!
Having a browse on the web, I can only seem to find...
complex coefficient fir matlab
Please can someone explain the benefits of a FIR filter with complex coefficients, as opposed to one which uses real coefficients? Why would I choose a complex FIR over a real one? I have seen complex FIR filters used occasionally, for example in equalization, but...
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