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Recent content by sirricky

  1. S

    on-chip balun's output imbalance problem

    yes, i think the main reason is just as you said. the siganl in primary coil was coupled to secondary one. the phenomena was worse at high freq than low freq, which also show the effort of capacitance coupling. But the coupling is along the whole coil, which is distributed, the quantitative...
  2. S

    on-chip balun's output imbalance problem

    since i could not upload the pic, i'll try to explain it more clearly. the balun was 1:1, the primary coil was a one turn indcutor with top metal, the the secondary coil was the same pattern as primary coil but was the another metal layer. so the layout is fully differntial, and no metal...
  3. S

    on-chip balun's output imbalance problem

    I designed an onchip balun to fullfill the single to differential convertion at output. the self-inductor was about 0.3nH. and the operating freq. was about 18G. the balun differntial output had a center tap, which should be connected to a AC ground. I found that if the center tap was not...
  4. S

    How to determine the specifics fulfilled WLAN or GSM????

    I am familiar with the RF front end circuit design,such as LNA, mixer and so on, but it puzzles me that how to determine the specifics (e.g. Gain, bandwidth, Noise figure, IIP3...) for the RF front end receiver which fulfilled the standard or protocol such as WLAN? I think this problem is...
  5. S

    connection of CPW and Microstrip line in Sonnet

    So nice!! Thank you all, I will have a look soon!
  6. S

    connection of CPW and Microstrip line in Sonnet

    Hello everyone, 1. since the ground plane of microstrip line is in different layer with the center line, assuming the CPW line is in layer 1, the center line of microstip is also in layer1, and the ground of microstrip line is in layer2, how could I set the ports? on the CPW side, I set as...
  7. S

    What are the salaries in Europe of an analog/physical layout engineer?

    salaries in Europe in Germany, about 4K Euro/month for a graduate student (first year)
  8. S

    HELP!A Problem in SPICE!

    i want to simulate a model of MOS transistor, for the VCCS, the expression is I=gm*Vgs, and gm=gm0*exp(-jωτ), where τ is a delay constant,ω is the operate frequency. But how do I descripe exp(-jωτ) in netlist, which I write it in HSPICE or ICCAP ? Any idea is welcome!
  9. S

    Looking for study materials about Agilents ICCAP

    iccap site:edaboard.com Can anybody offer some studing materials about ICCAP except for the user guide? I am a beginner on MOS Modeling, and any instrument and advice is welcome!
  10. S

    Question about hot carrier effect

    how dose the LDD structure work on avoiding the hot carrier effect in mos?? not quite clear, thanks
  11. S

    What's the process "cs080" ?

    i want to design a LVDS Driver/Receiver in 0.5 um CMOS, the speed achieving a few hundreds mbps is ok, which is similar to DS90LV019, but the datasheet said the process of DS90LV019 is "cs080" . i really puzzle about it , what's cs080? Thanks in advance!

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