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Hi suresh
can u give me some links to papers on leakage reduction with MTCMOS. I want to know how stacking multiple vt transistors can reduce leakage like stacking a low vt device on a high vt device??
Please send me link to some papers.
Thanks
Singu
I have characterized a D Flipflop with set and reset in Signalstorm and have converted the output from Signalstorm to a ".v" verilog file useful for simulation. But when i simulate the synthesized code with this .v file I get an error because of negative hold time value for the D flipflop.
I...
There is an option in icfb to import verilog files and convert them to schematic. In the icfb command window select File-->Import-->Verilog and this will display a window. U need to enter the Target library name where u want the schematic to be created, reference library is the name of the...
Re: I need to do Standard Cell Characterization and Modeling
There is a tool called Signal Storm Library characterizer in Cadence which is used for the automatic characterization of standard cells based on various conditions such as output loads, input slew rate etc...
internal power for characterizer
Hi
I am working on creating a standard cell library. I am attaching a conference paper done by me which explains the steps involved in creating a standard cell library.
If u have any questions pls mail me.
You should not connect the substrate to gate. That is a bad idea. Usually they are connected to VDD or GND. But by varying the VSB( Source to body voltage) we can change the Threshold voltage of the device becos of the dependence of Vt on body effect. If VSB is not equal to zero there is a drop...
Usually to make the rise and fall times equal and also to get equal drive strength from both the PMOS and NMOS we make the width of the PMOS either 2 or 3 times wider. For example if the NMOS width is 3um the PMOS is made 6um-9um wider.
We also need to do beta matching to get equal drive...
Hi,
I would like to know how to design a D FlipFlop using AND-OR-INVERT gates instead of using NAND gates. I have to do a small project on this and analyse the flipflop built from AND OR INVERT gates. Please give me an idea of the working principle.
Thanks
Singaravelan
low vt high vt
Hi,
I went through a couple of papers on Multiple Vt CMOS structures for low power design. In all of these they say that scaling down supply voltage reduces power consumption as
Power α (VDD)^2.
But as we scale down supply voltage we also have to scale down Vt.
I...
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