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Recent content by Sindhiya C R

  1. S

    System verilog Compilation error

    Hi, We can use typedef inside the class for include another class. I am having class as base,and interface as network and I have instantiated this interface inside the base class..While compiling this base class it showing error in interface instantiation I tried as below..But it shows error...
  2. S

    UART protocol Half duplex

    Actually I am in verification.I need to give input to UART Half duplex present in design for which TX/RX collision is controlled by software.So for that in testbench I have to use one Half duplex UART to give serial input to UARTpresent in RTL.I am having UART model with Full duplex mode..I need...
  3. S

    UART protocol Half duplex

    Hi I am working on UART with half duplex serial communication can anyone tell me how could be TX/RX collision(means direction) of UART is controlled via software if it is half duplexed? Thanks!!
  4. S

    Encryption and Decryption

    Thank you sir, my email id is raji20191@gmail.com
  5. S

    Encryption and Decryption

    Hi ,Can any one pls help me to understand DES engine and DVB engine for DEcryption of Transport packets? Thanks in Advance
  6. S

    Verilog - Files management

    Thank you Dave - - - Updated - - - Thank you ,I find it is very helpful
  7. S

    Verilog - Files management

    Hi ,Can any one please tell me the usage of $ftell and $getc in verilog? Thanks in advance
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