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A Higher transition time increases gate delay and also setup requirement of the next flop. But it need not increase hold requirements.
The definition of hold in STA is different - it means that the data clocked in the current clock cycle at the previous flop must NOT reach this flop in the same...
Re: virtual clock
There is a good post on Virtual clocks at
https://loxos.blogspot.com/2005/04/timinganalysis-why-virtual-clocks.html
What do you think of this explanation?
I think it is DFM - Design for Manufacturing.
At sub 90 nm levels, chipd yields are going lower and lower. I think DFM is the next hot field to come up
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