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Recent content by silver_kiss

  1. S

    what is specman tick mean?

    sync+specman For each simulation delta cycle in which a change in at least one of these monitored expressions occurs, the simulator passes control to Specman Elite. If simulation time has advanced since the last time control was passed to Specman Elite, Specman Elite issues a new_time event. In...
  2. S

    verilog dynamic instantiation ??

    there is no short cut u hve to write it but internal signals u hve choice to use or not
  3. S

    Help me with synthesis problems of a Verilog code

    Re: Synthesis Help read this might be helpfull for u
  4. S

    setup hold time violation in ISE

    xilinx hold time violations just go through this xilinx application note..basics of setup,hold
  5. S

    Compare Altera & xilinx's FPGA

    Xilinx is more easier and good than Altera, Xilinx is having more resources than Altera to play around the tool,device. Also xilinx supports memory read,write registered,but altera doesnt
  6. S

    Divide by 3 or Divide by n Counter

    design of divide by 3 counter just go through this!!! all the best
  7. S

    Bit stuffing bug in USB 1.1 Serial Interface Engine

    USB 1.1 bitstuffing bug Hi, I am debugging the USB1.1 Seriel Interface Engine. In this i found the bit stuffing error. but couldnot found the solution to fix the problem. Can anybody please help me in this regarding. Silver_kiss :)
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