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Recent content by silencer3

  1. S

    dc_compiler; uniquify

    Yes. You dont need to use any explicit uniquify commands as compile_ultra automatically uniquifies the design during synthesis.
  2. S

    [SOLVED] Timing ECO in ASIC design flow

    Functional ECO - to CORRECT/Change the design functionality after the implementation has started and dont have a chance to go back to synthesis Timing ECO - to fix all timing violations such as setup, hold, recovery, removal, DRV (max_fanout, max_capacitance, max_tranisiton)
  3. S

    Difference between .sdc and .sdf files

    SDC - Synopsys Design Constraints This file is used for all implementation tools starting from synthesis, timing analysis, place&route,dft,fpga..etc. This is very important file to ensure proper operation of your design, fpga, silicon SDF - Standard Delay Format Used to convey the timing...
  4. S

    what is RMW (Read Modified Write)

    read-modify-write rmw RMW can be explained with respect to its use. 1. RMW can be an instruction in some protocols. In such case, this has to be atomic (as exlained in the above post). 2. RMW is the process of Error correction in the ECC based designs. When data is read from a memory with ECC...
  5. S

    How to report TNS in PT?

    check the solvenet for QOR script for primetime. this will give you the TNS
  6. S

    PrimeTime Timing Closure

    To get more accurate results, use SPEF. This will allow the tool compute the delays with high accuracy as the detailed parasitics are provided as SPEF. You can also read in the SPEF and write out a SDF using primetime. Then use the SDF for timing analysis. But the delays will be little off from...
  7. S

    DC output file usage and the full name of these file

    Synopsys DC database - DDC Setup Verification for Formality (actually this is script input to formality) - SVF STIL procedure file - SPF
  8. S

    What is meant by flip-flops with multiple clocks ?

    Mutiple clocks while doing the synthesis, DC will optimize for all clocks (as we generally dont specify the case analysis). for example, if a flop gets both the test clock and functional clock through MUX; this means flop can operate on multiple clocks. to enable this capability in DC, set...
  9. S

    about critical path and report_timing

    report_timing on clock to get the reg2reg timing, 1. set_false_paths -from [all_inputs] set_false_paths -to [all_outputs] 2. use group_path and group all inputs and outputs (except input & output clocks) into one IO_PATHS group. now it shows reg2reg as one group and io paths as one group...
  10. S

    Unmapped point when doing LEC

    unmapped point in lec simplest thing is to provide the SVF file from synthesis. This will tell the tool what logic is removed, what is optimized and how its optimized. This resolves most issues.
  11. S

    how do people doing logic synthesis give SDC to back end

    DC is used for synthesis and its only for setup. so, if your DC constraints are only for setup; then you will have to define both setup and hold constraints for back-end. if input to DC is full constraints, then SDC from DC will do the job. back-end needs both setup and hold constraints, no...
  12. S

    Which cell delay to use when calculating data arrival time?

    cell delay tool will use the worst delay of a->y & b->y. In the cell both a->y and b->y may be same. So the worst path will be the one which has more load and worst transition. so, your input (a, b) characteristics will determine which is the worst path.
  13. S

    What is .tf file?. What does it contain?.

    .tf file TF file is ASTRO technology file. This contains all the information of the process, layers (metal & VIA) and all their charecteristics.
  14. S

    What is the difference between Macro & Standard Cell?

    Macro & Std Cell standard cell - basic logic cells macro - a function created from the standard cells. an example would be "clock gating cell" Hard Macro - An IP placed and routed which can just be used in a chip.
  15. S

    hich type of RESET(asyn or syn) will you prefer?

    Reset Best Solution is "Assert RESET asynchronously and De-assert Synchronously" Active Low or Active HIGH? If active high reset is used, any noise on the reset line can cause a spike and this results in a reset. But if active Low reset is used, this can never happen. So active low is...

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