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Functional ECO - to CORRECT/Change the design functionality after the implementation has started and dont have a chance to go back to synthesis
Timing ECO - to fix all timing violations such as setup, hold, recovery, removal, DRV (max_fanout, max_capacitance, max_tranisiton)
SDC - Synopsys Design Constraints
This file is used for all implementation tools starting from synthesis, timing analysis, place&route,dft,fpga..etc. This is very important file to ensure proper operation of your design, fpga, silicon
SDF - Standard Delay Format
Used to convey the timing...
read-modify-write rmw
RMW can be explained with respect to its use.
1. RMW can be an instruction in some protocols. In such case, this has to be atomic (as exlained in the above post).
2. RMW is the process of Error correction in the ECC based designs. When data is read from a memory with ECC...
To get more accurate results, use SPEF. This will allow the tool compute the delays with high accuracy as the detailed parasitics are provided as SPEF.
You can also read in the SPEF and write out a SDF using primetime. Then use the SDF for timing analysis. But the delays will be little off from...
Mutiple clocks
while doing the synthesis, DC will optimize for all clocks (as we generally dont specify the case analysis).
for example, if a flop gets both the test clock and functional clock through MUX; this means flop can operate on multiple clocks. to enable this capability in DC, set...
report_timing on clock
to get the reg2reg timing,
1. set_false_paths -from [all_inputs]
set_false_paths -to [all_outputs]
2. use group_path and group all inputs and outputs (except input & output clocks) into one IO_PATHS group. now it shows reg2reg as one group and io paths as one group...
unmapped point in lec
simplest thing is to provide the SVF file from synthesis. This will tell the tool what logic is removed, what is optimized and how its optimized.
This resolves most issues.
DC is used for synthesis and its only for setup. so, if your DC constraints are only for setup; then you will have to define both setup and hold constraints for back-end. if input to DC is full constraints, then SDC from DC will do the job. back-end needs both setup and hold constraints, no...
cell delay
tool will use the worst delay of a->y & b->y.
In the cell both a->y and b->y may be same. So the worst path will be the one which has more load and worst transition. so, your input (a, b) characteristics will determine which is the worst path.
Macro & Std Cell
standard cell - basic logic cells
macro - a function created from the standard cells. an example would be "clock gating cell"
Hard Macro - An IP placed and routed which can just be used in a chip.
Reset
Best Solution is "Assert RESET asynchronously and De-assert Synchronously"
Active Low or Active HIGH?
If active high reset is used, any noise on the reset line can cause a spike and this results in a reset. But if active Low reset is used, this can never happen. So active low is...
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