Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hey, thanks for your reply.
But it still remains a mystery why it has failed then. I thought one of the FET's in the output stage might have been forced to sink current in reverse direction, which caused it to fail. So what could the possibility.?
The chip had an enable pin for the LVDS txr...
Hi,
I am facing a peculiar problem. One of the designs I am working on, has an LVDS interface for data transmission. These cards are to be externally connected through a back plane. Each of these cards can be independently tested. Now when i power on one card to test its functionality, the LVDS...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.