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Hi all ,
Am designing a cap-less LDO/
While simulating at no load, stability of the circuit went totally loose. Although it is stable at any other load. Does anyone have an idea how to deal with this ?
Should I use a certain compensation scheme for the OTA, although it has enough phase margin...
Does anyone know how to simulate the PSRR? I have already put ac source, but it seems something is still wrong.
Also, can we use an ideal amplifier as a first trial? or we must test PSRR with a designed amplifier?
Thanks in advance.
Shrouk
Hey all , a question i couldn't find an answer for :
In simulating LDO to get LINE regulation , shall the load be only a capacitor or shall I insert a DC current source?
Thanks.
Shrouk.
Am new with linux thing and have no idea about commands, But the hotkeys are not working at all , does anyone know how to activate them ???
Thanks in advance.
I recently installed cadence but when i choose a technology file "tsmc13rf" doesn't appear,although i can see a folder with it's name. Does anyone knows how to make cadence read it ?
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