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Thank you so much for the reply. I really appreciate it. How about the other issue with the device iteself ? (I've attached a screenshot in my reply #)
Thanks again for all your input.
Hello,
After running the 65 nm code (the one you provided in reply #7), the structure seems to be turned off. Every thing else seems ok (threshold voltage, gate length, gate oxide thickness...etc) but this is the only thing that seems a little bit shady. I've attached a screen shot of the...
Thanks again for the much needed and highly appreciated reply.
The code for my previous analysis is as attached. It is merely example no. 8 of Silvaco examples, and is for PMOS. I've highlighted the statement that have been varied, which is the N-well implant statement.
On the other hand, in...
Hello again,
I've attached here a file that contains analysis of the effect of N-well implant on threshold voltage. I've varied the following parameters in the "mos1ex08.in : Id/Vgs and Threshold Voltage Extraction" Silvaco example:
1. Type of impurity:
---->amorphous Phosphorus...
Dear colbhaid
Thanks a ton! I hope you had very happy holidays :)
Here is a code for 100 nm process (it is based on Silvaco examples 9 and 8), it seems that everything is ok but the threshold voltage seems to be very large. Also, when I use two extract statements for Tox (1 right after gate...
Hello,
I am doing a project that needs me to design a PMOS transistor with 65 nanometer process using Silvaco TCAD tools. As you may know, there are examples provided in the software that I am using to customize in order to get the required dimensions.
Hence, I have to modify the Silvaco Code...
Thanks once more for the VERY elaborate and detailed help. I'm now very comfortable with gate length modification. I've tried modifying the following
1. Gate oxide thickness
2. Threshold voltage
for the gate oxide thickness, I tried to scale it down from (0.00371855 A°to 0.001A°, which is...
Thank you so much for the kind help Colbhaidh, I am really grateful.
Please allow me to ask the following:
Q1. According to ITRS (International Technology Roadmap for Semiconductors), we cannot just reduce the gate length (by the way, when we say for e.g a 65 nm p-MOS, do we mean the gate is...
Hi all,
I am doing a project that needs me to design a PMOS transistor with a channel length of 65 nanometers using Silvaco TCAD tools. As you may know, there are examples provided in the software that I am using to customize in order to get the required channel length. So, I have to modify the...
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