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Recent content by shmoib

  1. S

    VHDL 360, Create Your First Model for a Simple Logic Circuit

    I don't think std_logic type packages has vanished or will vanish in the near future, I still see different designs that uses these packages. As for slide 17, the std_logic_unsigned type -which is used in the example there- already includes the std_logic_1164 thus no need to include it again. I...
  2. S

    DSP processors, whats are ?

    Hi, check the following link, it contains a useful information about DSP and FPGA **broken link removed**
  3. S

    Problem with cable connection while programming Xilinx FPGA kit

    Re: help needed i think this may arise if you are not the host admin
  4. S

    How to generate FSM for a 3 but parity generator?

    Re: how to model FSM you dont know the coding style for FSM, or you just need someone to give you the state diagram for this operation?
  5. S

    Looking for unix shell emulator for Windows

    dear all, i'm searching for a unix shell emulator that could run under windows, i just want to try unicx shell commands. thanks in advance.
  6. S

    Looking for docs on microwave devices like Klystron or TWT

    microwave devices i need any document about microwave devices like Klystron and TWT. thanks in advance
  7. S

    Error, No implementation available for divide

    try to loop on subtracting the second one from the first and calculate the result from number of loops.
  8. S

    Mealy FSM Serial Adder using StateCad <= Help Needed

    serial adder mealy why dont you write the code directly , it will give you more abilities
  9. S

    Introducing delay in signal??? need help...

    you can simply route the one you want to delay in a longer path. or you design your special inverter with W/L that gives you .7 ns.
  10. S

    What's the clock frequency of FSM that controls action of other blocks?

    Re: FSM clock the FSM is used for a control unit, which is supposed to take decisions upon output of the controlled blocks, so it is supposed to run faster so that it can enable or disable other blocks without clock missing.
  11. S

    What's the difference between architecture and process ?

    Re: Confused!! yes, u cant write sequential statment directly inside the arch.. without a process, as the anything written inside the arch. is considered as a concurent statment while all inside a process is a sequential, if u use two processes they will be concurent with each other but each...
  12. S

    Help me fix Xilinx warnings: outputs are unconnected in block

    Re: xilinx warnings. it seems that u r using schematic editor to connect ur blocks, anyway, try fist to synthesize each block alone and check the warrnings associated with each.
  13. S

    quick frequency division problem

    i think it is better to use DLL or DCM cores if u r using xilinix chip
  14. S

    What's the clock frequency of FSM that controls action of other blocks?

    Re: FSM clock thnks, i tried to work with the same freq. but it givebad result, while when i work with 8 times the frequency it gives a good solution. i'm using this FSm to control digital block working at same freq.
  15. S

    Safe way for taking 12V directly from car battery

    Re: car circuits in this case, if i'm going to use fuse directly it will blow every while. zener will do same as voltage regulator,
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