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Recent content by Shishira

  1. S

    Element for producing half and one clock cycle delay in Cadence

    Sorry for using the wrong notations, my question is restricted to the analog side. By n-1 , I just meant adding with the previous value (which is noting but delayed signal.)
  2. S

    Element for producing half and one clock cycle delay in Cadence

    Okay, that sounds deep thanks. I actually need two output signals, a) 0.5 (half ) cycle delay b) 1 (one) cycle delay 1645017458 Hi, Yes that's right, so there is no other way to delay the signal? I want to have an algebraic addition of these signals, say x[n] and x[n-1]. Fig is from Simulink model
  3. S

    Element for producing half and one clock cycle delay in Cadence

    The signal is , * fixed frequency say 32 MHz * It's not a clock signal, it's a correction signal extracted for further operation. (It is sampled w.r.t to a clock signal of frequency 32 MHz) * Vout range -500mV < Vh < 500 mV This is a discrete signal and can take any value between 500mV < Vh <...
  4. S

    Element for producing half and one clock cycle delay in Cadence

    Hey, that sounds promising thank you. But, attaching a second S&H should give a delay of 1 clock cycle isn't it?
  5. S

    Element for producing half and one clock cycle delay in Cadence

    Hi Klaus, The problem is to get a delay of 0.5 and 1 cycle delay. Yes 1.5 cycles is not useful
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    Element for producing half and one clock cycle delay in Cadence

    I already have a SC circuit in feed-forward path and hence I do not want to increase area and power. Isn't there any other simple way?
  7. S

    Element for producing half and one clock cycle delay in Cadence

    Hi All, I want to introduce a delay of half and one clock period in an analog circuit. I need an element/circuit that can produce half-clock period in real circuit to be taped out. I cannot use a D flip flop as the output needed is an amplitude varying square signal. (atch 2). Looking forward to...
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    [SOLVED] Sigma delta modulator desin in Simulink

    Hello, I am working on understanding system level design of delta sigma ADC and came with this beatifull book 'Design of Sigma-Delta Converters in Matlab®/ Simulink®' by Isacco Arnaldi. The author has given a toolbox link within the book, but unfortunaltely the link takes us to a mathwork file...
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    Current reference design for CS-DAC

    Hi Dominik, Definitely I will try the steps suggested by you. a)The biasing transistor for HSCM is 1/4 or 1/5 times to that of current source or cascodes ? b) For now, I have kept it 1/10 th (to push it more into saturation) to that of current sources in nmos stage and all transitors seem...
  10. S

    Current reference design for CS-DAC

    The wp/wn ratio is 2, both for cascode and mirror transitor with respect to its nmos counter part. Should I still decrease the ratio or increase ?
  11. S

    Current reference design for CS-DAC

    Hi All, I am designing a reference circuit for the current steering DAC. The current provided is 10 uA and I need a current of 500nA as LSB current. I decided to take up PMOS based DAC with nmos cascode current mirror as its reference (as shown in the figure). I was able to achieve the design...
  12. S

    Biasing of wide swing current mirror

    ---------- a)So, the cascode transitors have to be bigger than current mirrors, so that they have lower Vdsat ? b)In the above figure, what is the general relation between W/L and Wc/Lc ? c) The stacked transistors --> Wic/Lc (bias section) in figure, has to be 5 to 6 times smaller with resprct...
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    Biasing of wide swing current mirror

    Hi Sutapanaki, I did try to bias my PMOS wide swing as per your suggestion ( Vov is 200mV), I had few questions 1) How to select the widths of stacked transistors used for biasing ? I kept the lenghts same as that of cascode transistors. 2) How to select the size of cascode transistors in lower...
  14. S

    Plot lambda vs length in Cadence

    @dick_freebird Could you please elaborate the procedure? The steps to do, 1) Id vs Vds plot (dc sweep of Vds) and take lambda expression into calculator(for which w/L should I take the lambda expression?). 2) parametric sweep for different length on same Id vs Vds plot? does it work, because I...
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    Folded cascode OTA design

    Could you tell me what is inversion coefficient that should be used for calculation ? The pdk documentation is the " .scs " file of that transistor??
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