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Recent content by shield

  1. S

    [help] need USB design by example, second edition

    usb design by example USB Design by Example: A Practical Guide to Building I/O Devices (2nd Edition) (Paperback) by John Hyde (Author) Paperback: 510 pages Publisher: Intel Press; 2nd edition (February 2001) Language: English ISBN-10: 0970284659 ISBN-13: 978-0970284655 Product...
  2. S

    about ise batch application

    hi,all I use the following tcl script.The "map" always do twice This is timing-consumed. what cause this? Thanks in advance #tcl script projec new project.ise #device set #add file # set properties process run "implement design" process run "generating congfiguration file" project close
  3. S

    [Req] How to do Clock Domain Checking(CDC)?

    this is a hard jobs to use tcl to check CDC? who has the scripts?
  4. S

    What is the purpose of the tcl/tk in VHDL?

    tcl/tk good materials, but search it in the web is so hard
  5. S

    i want different between USB and PCI

    pra's explanation is more reasonable. The USB3.0 protocol refers to the PCI-e architecture
  6. S

    estimation of gate count

    And are there anybody explain how to caculate the count for FPGA and ASIC of the same count?
  7. S

    about I2C signal in cpld

    i2c signal hi, all I need to connect the E2PROM with the FPGA with I2C interface through CPLD? How I should implement this function? thank you
  8. S

    how to add delay for sram?

    Hi, all I need to register the signals before they connected to dual port sram. How keep the delay at two clcok domain the same ? thank you!
  9. S

    The question about DC synthesis!

    I have also meet similar question. whether there are some tutorials about the dc systhesis script?
  10. S

    abot the frequency ppm

    frequency-ppm how to test the frequency acurate in the fpga platform
  11. S

    about the memory efficency

    in consumer electronics , usually use a core based platfrom for the time window. But when the peripherials increment, the memory access is becoming an bottleneck. So I want to ask whether there are some methods to improve the memory access effiency ?
  12. S

    about dma controller effiency evaluation

    whether are some method to compute fo this?
  13. S

    how to test usb mass storage transfer speed ?

    test usb transfer speed hi ,all Is there any one know how to test USB mass storage class transfer speed on FPGA prototyping? And how the difference between on FPGA and ASIC ? Thank you!
  14. S

    ASIC / FPGA , VLSI presentation

    this topic is too large ,even if you have worked for serval years at this field

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