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Okay sorry, I overlook when typing this. Metastability output will be X.
Synchronizer only lower metastability probability but the output still can be wrong (as defied logic).
Is this correct?
When metastability happens, then it is possible?
This is what i am asking. Putting synchronizer only guarantee output is defined signal (0 or 1) but it does not guarantee it is the correct output.
If metastability happens, the output still can be wrong but it is a defined signal. Is this correct?
Wrong data to me is unexpected output. Let's say I am sending in a '1' to synchronizer and the output is '0'. To me, this is wrong output value.
The reason I am asking this question is IF input data frequency is different with destination clock frequency, when you fail to sample then it will...
Hi all,
After reading many posts in the forum, I started to get confused.
My understanding on metastability is it cause the output to be X. This mean it can be any values.
By having high MTBF, we have high probability to avoid metastability.
My question is does this mean we will have a correct...
MOSFET acts like a switch and it is opened when vgs < vth but closed when vgs > vth.
From simple MOSFET equation, ignoring body effect and etc.
When Vds < vgs - vth it acts like a variable resistor. Current allowed to pass through will be directly proportional to Vds.
But when Vds > vgs - vth...
I don think it can work async. The waveform is correct corresponding to the schematic which is only can be reset when clk is falling edge.
If you want something async, why don't you put a pmos on top of M9 and change M10 connecting output and ground. This can surely pull output to '0' whenever...
I assume when you say it doesn't work means your output is a flag dc signal?
I suggest you to probe the in/output signals of each IC and check which signal is not in expectation for debug purpose.
Just my guessing.
The clk pass through delay lines and sampled at the latch(i think it should be a flipflop instead of latch) of a refclk. With the refclk, we can get a code which representing how big is the delay of delay lines.
The control unit is hard-decoded into two bits, still...
Yes. I did go through HSPICE documents. But seem like it takes bisec method which might not suitable for a nonmonotonic function.
Could you provide me with some examples?
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