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Hello,
I am new to power analysis in digital ASIC. My question is how to properly use the power report numbers to get the requirements for the LDO and decoupling capacitor that supplies the digital block
Assume I have the following numbers:
internal power: 8mW
switching power: 1mW
leakage...
How did you make the simulation for the original verilog code?
It should be the same, but you need to first compile the standard cells library file then compile the output netlist from the layout tool. Also note that you may not see internal signals of the block because the netlist may have...
Hello
I am new to DFT and I want some help with the following long issue
A design has 3 clocks A, B and C with frequencies 100MHz, 50MHz and 20MHz respectively. All clocks are asynchronous from different clock sources. All three clocks are used in the block. Paths between clocks can be...
As "c_mitra" replied, complex math functions are calculated using numerical methods. This question is not about verilog or digital design. You can search on how to calculate the log or ln or whatever using some additions/subtractions/multiplications/division then you use HDL to implement this.
In the compile menu in modelsim, select "compile options". Under VHDL tab, under "Check for" enable the checkbox "synthesize". When you run the command "vcom" for vhdl files, you will find few warnings like missing signals from the sensitivity list.
Sandy2811, in the code you provided, you need to change the "always @(posedge clk)" to be "always @(posedge rst or posedge clk)" to see the effect of "rst" in simulation
Have you tried https://www.cygwin.com/?
It provides tools similar to what you can find on linux. It has the "sed" command and other useful stuff that exist in linux.
Thank you filip.amator
I did not select the ADC chip yet. The expected interface is LVDS. All the channels are synchronized.
For the RAM, I may need to add DDR3.
I already made boards with ADC/DAC with FPGAs, but my question is about your recommendation if the sampling rate is more than 150...
I am about to select an FPGA for a system in which there are two ADCs with sampling rate more than 150MHz.
There are many choices for the FPGA model. I can use Altera or Xilinx.
I want to select the best FPGA model for this purpose. I can select from (Altera) Cyclone 5, Arria 5 or (Xilinx) Artix...
wesleytaylor, when you said "(with a bit file that didn't have loader & can comm bus)", did you mean that the hdl code of the FPGA has a certain custom block that can access the flash memory of the FPGA??
I once wrote my own custom HDL code to access the flash of one Altera FPGA to save some...
I wanted to evaluate USB3 communication with the PC with Cypress FX3. The evaluation board CYUSB3KIT-003 contains that USB3 chip. I wonder if anyone here has used this chip before with FPGAs. Will this evaluation board be enough?
Thanks
As said in the standard, you can set default value in the entity declaration like
input_data : in std_logic_vector(7 downto 0):= "00000000";
If you left that port (input_data) open, no error will be reported. You do this in the component declaration on the parent design block.
Your question will require a very long answer
But first,
Does your board have external memory?
If it has one, learn first how to interface with it and store data there and read it back.
If it does not have, check what the available memory size of the FPGA chip is.
After that, how big is your...
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