Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
okay, thanks for the answer.
do you know if there's any problem with the floating 5V mosfet, while it gets high voltage (of 100V)?
I mean drain or source voltage, or the risk is only depends on voltage drop between drain to source(or opposite)?
Hi all,
I'm trying to understand whether it is possible to "float" a circuit?
How can I manage doing that?
the circuit is combined with 5v pmos and 5v native nmos.
the VDD suppose to be 100V and VSS 95V
the voltage drop over all mosfets is around 5V (Vds, Vgs)
if I use deep N-Well all around the...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
