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Re: calibre error
This is a clear case of not giving GDSSII file for some (which are giving errors) cells which are present in design but not in GDSII.
Solution is, either merge GDS of all cells/macros/blocks OR specify GDSII files for cells/macros/blocks in caliber run
Re: Reg: Physical Design
firewire2035 Is right. But just for check, have you done scan reordering? If not then, this is a main culprit for such a high density. I faced this problem at initial stage of my career :wink:
Re: soc encounter error
I think the problem with your "globalNetConnect" command. Check your name of standard cell PG pin, it will be “VSS” not “gnd”. If it is VSS then try this command
< globalNetConnect VSS -type pgpin -pin VSS -inst * -module {} –verbose >
If you have given same command...
Re: Temperature Effect
If you mean to say clock speed is max clock frequency.
Then it is going to reduce with increasing in temperature, because cell delay will increase with increasing in temperature.
And max clock frequency will increase by increasing in power sources, because IR drop...
I have never used any equation for STA. so I cannot put explanations in equation properly. I will try to put some rough equation
Required time = clock cycle + skew – setup time of a flop
Setup violations = required time – arrival time
So if your skew is negative, required time will be less...
Negative skew means, clock is reaching capture flop is faster than the launch. So you have small timing window to meet the timing. In other words possibility of setup violation will increase, so ultimately your frequency will reduce….
Hope explanation is clear enough….
max_cap and max_tran violations
Another reason to fix transition violation is, Library will be characterized till certain value of transition. If you are exceeding that value then your library will not be having delay information in look up table for that transition. So whatever timing analysis...
scribeline sealring
Seal ring is to give strength to the die, and scribe line is margin for wafer cutting. Rough figures are abt 15u from pad, all sides (combining sealreing & scribline)
Rahul
how are hvt transistors made
For timing critical path low Vt cell is better, but at cost of more leakage power.
For non timing critical path High Vt cell is good choice
Re: Low-power design
Good work denmos,
I think we need this topic to be discussed thoroughly.
I have one doubt in this equation {P(dynamic) = a x F x C x sqr(Vdd) }. what is "a" here? and in delay calculation also.....
waiting for your Sesson-2 :wink:
i have faced this problem b4, for this u need to make some changes in map file for "TEXT" and additional to that
some setting for streamout command and virtuoso, it goes like this
Step 1: In FE while streamOut use "attachNetName" with any attribute number
streamOut -attachInstanceName 102...
Reduce data path delay as much as possible. There are few techniques for that like
~ Up/down sizing cells
~ Adding/removing buffers
~ Changing placement of cells (except F/F after CTS)
~ Decreasing crosstalk delay by spacing/widening routing
etc…
Re: reliability issues
I would like to add few more....
Hard errors:
~ Latchup.
~ Electrostatic discharge.
~ Hot carrier effects.
~ Thin dielectric breakdown.
Soft errors:
~ SEU (Single Event Upset)
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