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Recent content by shawndaking

  1. S

    Chipscope analyzer problem with buffered data

    Re: chipscope problem so i understand you are not working with the debugger at all ? is your cpu works correctly during this time or it crashes ?
  2. S

    Regarding dualport RAM

    you need to elaborate : what is "output not coming", what exactly is the ram you are using, and how you connect to it.
  3. S

    Chipscope analyzer problem with buffered data

    Re: chipscope problem i had phenomenas like this in the past, look like your system is instable. are you debugging a cpu code right now, or anything that can distrupt your jtag connection ?
  4. S

    EDK and GDB - Code does not run

    i think it is good to have a reset pin. don't know how you cope without it.
  5. S

    EDK and GDB - Code does not run

    its the only one to be marked after that you must do the update bitsream command. the program start address is when defaul linkerscript is marked. you can also add stach, heap size but this is the most important.
  6. S

    How to implement y=sinx in VHDL?

    Re: VHDL code this is from xilinx coregen lib :
  7. S

    Chipscope analyzer problem with buffered data

    Re: chipscope problem are you sure your jtag connection is ok, are you using it for other task at the same time like for gdb ?
  8. S

    EDK and GDB - Code does not run

    edk gdb debug options your first problem was probebly due to jtag chain. for your current problem : 1. have you put the start address - normally you put 0x100 - don't let field to be empty !. 2. also of course you should mark the booloop for bram initialisation <green>, and your application...
  9. S

    How to include Virtex2 Pro Library in my design?

    Re: Library including..headache!! warnings are not so bad as long as you don't get any errors !?
  10. S

    VHDL: Truncate signed to std_logic_vector

    vhdl signed to std_logic_vector well in this case i would use a function to do the truncation , and put it in my package.
  11. S

    VHDL: Truncate signed to std_logic_vector

    std_logic_vector signed i think this is a case when you are trying to fit a bigger tube for your tire.
  12. S

    How to implement y=sinx in VHDL?

    Re: VHDL code you can do it by : 1. preparing ROM for the calculation with all values defined. 2. in xilinx you can use CORDIC core for generating this function. 3. if your input is more limited to specific values, you can even use a decoder to decode the values.
  13. S

    hardware speed vs software speed

    however software design is much much faster then hardware. the main reason are : a. software code is more common (open sources, libraries ). that means it is very easy to take software packages or libraries and integrate them. b. software languages are more advanced - c, c++ jawa to hw...
  14. S

    active low reset or active high reset

    Re: Assert or Deassert Reset i agree with vsmguy : this kind of question is to filter which one really has experience with design then one that has not. what he actually expect from you is to clarify, or developp the issue further more, thus you generate an interaction, which is most importent...
  15. S

    How to Synch. two Diff clock.

    if ignoring the skew isues : i think what he really wanted you to say is that you will use 2 bit bus as output with the 50khz clock, i.e to demux the data1 input ! so you use the clock2 as selector to 1:2 demux device that select the data1 input !!! best regards !

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