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If it sinks current would the value of the current be large enough for large drop on the pull up resistor thus potential between CMOS gate would be 0(wrt to ground). am i right?
then what would happen if the output of ttl gate is low ? (transistor of the ttl gate would sink current the same case would happen as you said the current through the resistor would be minimum and hence output would still remain Vdd)
hey guyz,i wanted to know that for a bjt to work as an amplifier the Q point should always be along DC load line preferrably on the centre now the problem is what will happen if the Q point is selected in such a way that it is little bit away from the DC load line :???:
"In BJT configurations, the term "COMMON" indicates the transistor terminal that is grounded. Often these configurations are also referred to as Grounded Emitter/Base/Collector configuration."
sir if that is true then in case of CC the collector isnt connected to ground.In the diagram the...
sir but how to know from here that emitter is common to input and output is there any reason it can even be CC and what about Q3 and Q4.is Q1 connected in CB config?
hey guyz,in the diagram there is ttl not gate given.i wanted to know in which configuration(CB,CE,CC) is the transistor Q2 connected and how to determine that.
**broken link removed**
guyz after seeing this explanation on sr flip flop i have a doubt related to it,
how can a two input nand gate give output using only one input at a time?
i have doubt that when we plot the input characteristics of a transistor (in CB configuration) why do we keep Vcb constant and not Ic and in output characteristic why do we keep Ie constant and not Veb.is it a convetion or is there a reason?
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