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Recent content by sharas

  1. S

    Configurable delay, constant with respect to voltage and temperature

    Hi, Sorry. I was talking about an asychronous system. My intent is to be able to create a delay difference between 2 signals at a range between 0-250ps, with a 10 ps resolution. I have a low frequency refernce clock.
  2. S

    Configurable delay, constant with respect to voltage and temperature

    Hi, I am trying to design a configurable delay cell, where the delay is not a finction of the supply voltage and the temperature. It can be influenced bt the process. It needs to be low power and small in area, so an ADLL is diqualified. Can anybody give me a clue...
  3. S

    Extracting effective mobility in hspice

    Hi, I am trying to find out what is the effective mobility my model has for a mosfet device in different temperatures. I tried .print ueff_n=par('lx132(xcirc0.xI50.m7)') But this gave 0. Any help will be much appreciated. Thanks...
  4. S

    pre emphasis with voltage mode driver

    Thanks dick_freebird. But doesn't that chnge the output impedance during operation (a thing that I would like to avoid in order to prevent reflection from the line)? Thanks, Sharas
  5. S

    pre emphasis with voltage mode driver

    Hi, I want to implement a "pre-emphasis" feature in my voltage mode driver, but I can't see, to do so without violating the output impedance requirement. Does anyone have an idea? Thanks, Sharas
  6. S

    linear system with a zero in the transfer function

    Thanks guys for the replies. I understand Zorro's reply: That means that for a pure sinus casuality is indeed vilolated? LvW, can you please elaborate hoe this solves casuality in the time domain for an idiot as myself? Thanks, sharas
  7. S

    linear system with a zero in the transfer function

    Hi, If I have a linear system with a zero in it's tranfer function. This mean that the phase of the output will precede the phase of the input. How is this possible ?? Thanks, Sharas
  8. S

    Need material on pre emphasis circuit

    site:edaboard.com pre-emphasis Hi, If anyone can point me to material regarding pre-emphasis circuits for high speed serial links, I would be grateful. Thanks, Sharas
  9. S

    Intuitive explanation for gmb

    Thanks sutapanaki! This was a great explenation.
  10. S

    Intuitive explanation for gmb

    Thanks, but outside the math, what's the physical explanation for this current source?
  11. S

    Intuitive explanation for gmb

    idsat square law prove I am having trouble understanding how, in the presesnce of body effect, the resistance looking into the source of a mosfet is reduced. Why is body effect modeled by a current source between the source and the drain? I thought it just shifts Vth? Thanks in...
  12. S

    Strange results when simulating circuit at ss cold corner

    Hi, I am witnessing some weird effects in my circuit (part of the circuit speeds up more than the other) when simulating at ss at 0 degrees. (65nm process) Is anyone familiar with this corner? what can be the reason for such strange behaviour? Thanks, sharas
  13. S

    What utilization are users seeing at 65nm?

    Re: 65nm utilization maximum 67% cell row utilization using Magma, but it depends on your design.
  14. S

    Checking power rail continuity

    Hi, Does anybody know how can I check that I don't have any "holes" in my power rail in Magma?
  15. S

    Why do we insert antenna fillers into a chip?

    Re: Antenna fillers Thanks. In my company the methodolgy is indeed to place these spare antenna cells.
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