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Recent content by shanmugaveld

  1. S

    Writing a good HDL code?

    For VHDL coding styles, I prefer "VHDL coding styles and methodologies by Ben Cohen"
  2. S

    Regarding reset pin in the Design

    Reset pins are used to put all your registers, FSM states into known state. if (reset == 1'b0) a <= 1'b0; else a <= b; a - output; b as input.when reset is applied a will be assigned to 0. a will not vary wrt b until reset is removed.
  3. S

    Verilog code error I can't define!

    For loop is synthesizable only. for loop, if statements should be within always block. put "count" also inside always block. without using assign. Do this changes along with what "FboDigit" suggested.
  4. S

    synchronous and Asynchronous Reset

    1. Synchronous reset will consume more area than asynchronous. Check this links https://asic-world.com/tidbits/all_reset.html 2. synthesizer can able to infer synchronous reset.
  5. S

    the `include file problem encountered when dealing with FPGA,VCS

    Consider below Directory Format, in which under RTL folder each directory has one file needs to be included Project RTL Func_1 Sub_func_1 Top Func_2 TB you can...
  6. S

    the `include file problem encountered when dealing with FPGA,VCS

    use "+incdir+<include path>" when you are compiling
  7. S

    Addition of a signed and an unsigned number

    check below pdf to work on signed and unsigned in verilog. **broken link removed**
  8. S

    How to test for Dont care bits in VHDL test bench

    use assert my_data[7 downto 0] = X"00" report "";
  9. S

    Clock switching

    Hi All, Came across an article about Techniques to make clock switching glitch free It may be useful **broken link removed**
  10. S

    Can we use functions in design ? if yes what will be the synthesized

    Each functional call will be synthesized as a separate combinational logic block.
  11. S

    verilog coding problem.

    Problem is for loop will give you end result only. It wont give intermediate results. You need to try some other way to get the results. example you can try FSM to track no of zero's for this. There may be some better way to implement this
  12. S

    problem in verilog code

    Then put outside the "for loop". In FOR LOOP output will be updated after one complete run. You cant see the intermediate results. Since you are assigning the counter value to zero, it overrides the original value. Even if you initialize the "o" as 1 also, it will give result as zero only
  13. S

    problem in verilog code

    if(i[j]==0) begin count=count+1; end else begin o=count; count=0; --- remove or comment this part and check. you are assigning count value zero here. It is under for loop. so it is causing the issue end end end endmodule
  14. S

    double flip flop synchronizer design for clock domain crossing

    we need to make sure that data 0 is atleast stable for two clocks in the receiver domain before sending 1. If the receiver fails to receive correct data, we need to use different type of synchronizer to get the correct value.
  15. S

    problem in verilog code

    Output is not initialized to any value. So it will take XX only. If you perform any operation with X's you will get x only. If it is synthesizable code use one pin to reset the value of registers else you can use initial(it will execute only once not always) or the way you have...
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