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Recent content by shailendra_gupta

  1. S

    What are the challenges we should face when we move to 65nm?

    Hi, As the technology shrinks the interconnect delays dominate over the gate delay. This is main challenge in lower technology node. Short channel effect comes into picture. Device will reach into the saturation even before pinch off. The VIA's resistance get increased as the technology shrinks
  2. S

    i want Encounter Test tool reference

    There is SOC ENCOUNTER user guide which will let you how to use the encounter tool. You may find it at yoour installation directory called doc. Also there is a command reference guide for the command used in the encounter tool

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