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DAC switch error
In case of R-2R DAC relatively larger width transistor to make the on resistance as small as possible.
the tradeoff are clockfeedthrough, charge injection missmatch with speed.
INL/DNL of Nyquist ADC
If you apply one positive going ramp and check:
{code(i)-code(i+1)} in terms of lsb. then it should increase by 1-lsb. so, if you substruct 1-lsb from it then you get zero. it makes DNL(i)=0.
All definition has the same meaning, only diferent in approach.
for missing...
You have to see your design specification to find the snd requirement for your application. you must check your input signal's band of interest.
If your system needs 18bit of dynamic resolution then you have to go for 108dB SNR ADC.
Static performance like DNL mainly tells you about Missing...
Hi all,
I am designing a high speed pipe-lined DAC.
I am using a differential folded cascode OTA with S/W capacitor CMFB(common mode feedback) circuit for each bit cell. the AC-analysis is showing a 60bd gain. but transient analysis is showing some gain error. in this case, gain is droping...
Hi ..
I think that you have a pole zero dublet near your unity gain frequency. that's why you r having a good phase margin and less good settleing behaviour.
there are one very important design choice:
additional gain stages need not be as fast as the main stage, and that the first order...
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